Algorithm Acceleration

Every algorithm decomposes into its data flow graph (DFG) and control flow graphs (CFGs). High-Level Synthesis (HLS) compilers try to generate efficient, fixed, CFG hardware. RTLs will allow you total freedom when designing each state machine you’ll need in your design, but RTL state machines are hard to program and hard to get right.

We used RTL to design the Hotstate machine, but it’s programmed using a subset of C. The code dictates the Hotstate machines’ resources used. If you only use a subset of the functionality, you get a subset of the Hotstate machine optimized to your code.

Uses for the Hotstate machine include, control data paths, bitbang controllers, parsers, low bit length neural networks, verification, instruction decoders, instruction sequencers, and many other tasks. If a softcore processor is overkill for your task then the Hotstate machine is for you.

Users of the Hotstate machine are HDL engineers that know a little C and want something done quickly, dependably, and of high quality. The Hotstate machine will save you time and money.

The Hotstate machine comes with published source hardware  code, so it can be ported to any hardware tool chain. The compiler, hotstate, comes in an x86 as well as Arm64 versions that can be run on an Arm based SoC. 

This is not a processor core. A processor core is always the same size which means that the program counter and register file are usually 32-64 bits. This slows down the hardware. If you have 256 lines of microcode, then you only need an 8-bit program counter. A processor core has a register file that might have 32 32-bit registers. A processor has an ALU packed with every opcode possible. With the Hotstate machine, you add just the right amount of data path RTL hardware and let the Hotstate machine(s) control that hardware. That might mean hundreds of adders and multipliers and registers or a single adder and FIFO controls, all controlled via software.

The Hotstate machine is a highly parameterized, microcode, algorithmic state machine. The Hotstate machine is programmed using a subset of C called CommaC. The compiler extracts the parameters for the state machine directly from the code and generates the microcode to implement the program.

The Hotstate machine supports all the control statements in C. The Hotstate machine also supports limited function calls and an interrupt vector.

Your code drives the architecture and the size of the Hotstate machine. Smaller programs generate physically smaller state machines that are faster and use fewer resources.

To implement concurrency, use multiple state machines. Each Hotstate machine has its structure driven by its program. Instead of one big state machine, several smaller state machines will be faster and take less resources.


/* Steve Casselman */

bool LED0 = 0; /* state0 */
bool LED1 = 0; /* state1 */
bool LED2 = 1; /* state2 */

/* inputs */
bool a0,a1,a2;

/* main loop */
if(a0 == 0 && a1 == 1)
LED0 = 1, LED0 = 0; //LED0 will equal 0
else if((a1 == 0 || a2 == 1 ) & !a0)
LED1 = 1;
if(a0 == 1 && a2 == 0)
LED2 = 1;
if(a0 == 0 && a2 == 0 & !a2)
LED0 = 0, LED1 = 0, LED2 = 0;
if (!a0) LED0 = 1;
} /* end while */

The hotstate compiler will create many files. When running the hotstate program, it will check to see if you have a makefile. If you don’t, hotstate will create one. You generate a testbench by using one of the options to generate different styles of testbenches, “make tbs” is the most efficient.

The hotstate compiler will generate a Verilog template file. In this file, you have the parameters that allow the hotstate machine to exactly match your program.

hotstate #(.NUM_STATES (3),.NUM_VARS (9),.NUM_VARSEL (4),.NUM_TIMERS (0),…


The waveforms below are taken from the parser example. Match the first while loop to the output of the analyzer.  

Here’s a shout-out to RTLvision for the use of their excellent schematic generation tools!

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