// Copyright (c) 2021-2022 HotWright Inc.
// Created Fri Sep 23 10:09:22 2022

// This is a machine generated file do not edit!
// copy it to another file name and use that in a design
// this file will be over written


 module parser_sm(
    /*input din0,
    input din1,
    input din2,
    input din3,
    input din4,
    input din5,
    input din6,
    input din7,*/
    // add bus
    input [7:0] din,
    input next_wrap_around,
    input valid,
    input clk,
    input hlt,
    input rst,
  //  input interrupt,
  //  input [4:0] interrupt_address,
    output read_data,
    output write_data,
    output next_data,
    output [4:0] debug_adr,
    output pop,
    output reg push,
   // output ready,
    output reg [7:0] dout);
  
//wire push, pop;
wire [2:0] states;
wire [9:0] variables;

assign read_data = states[0];
assign write_data = states[1];
assign next_data = states[2];
//
// add bus
//assign variables = { valid, next_wrap_around, din7, din6, din5, din4, din3, din2, din1, din0 };
assign variables = { valid, next_wrap_around, din[7:0] };

// The data path
reg next_data_r, write_data_r, pre_push, ppre_push;
always @(posedge clk) begin
  if (rst  == 1) begin
  next_data_r <= 0;
end
  else if (read_data ==1 && next_data == 0) begin 
  if (write_data == 1) dout <= din;
end 
else if (next_data == 1 && next_data_r == 0 && read_data == 0) begin
   dout <= 8'h0a;
  end
next_data_r <= next_data;
end

// changes in program written for fifo instead of for memory 
assign pop = (read_data) | (next_data & !next_data_r);// & !read_data) ;

always @(posedge clk) begin

  if (rst  == 1) begin
  pre_push <= 0;
  ppre_push <= 0;
  write_data_r <= 0;
  end
  else if (dout != 8'h0a && dout != 0 || write_data_r /*|(read_data == 1 && write_data == 1)*/ ) begin //this should be done in the hotstate state machine
  ppre_push <= write_data_r | (next_data & !next_data_r);// & !read_data);
  end   
  else begin
  ppre_push <= 0 ;
  end

  push <= pre_push;
  pre_push <= ppre_push;
  write_data_r <= write_data;

end


hotstate #(
    .NUM_STATES (3),
    .NUM_VARS (10),
    .NUM_VARSEL (6),
    .NUM_VARSEL_BITS (3),
    .NUM_TIMERS (0),
    .NUM_ADR_BITS (5),
    .NUM_CTL_BITS (18),
    .NUM_WORDS (23), // changed from 19
    .STACK_DEPTH (0),
    .NUM_SWITCHES (0), 
    .SWITCH_MEM_WORDS (0),
    .NUM_SWITCH_BITS (1),
    .SWITCH_OFFSET_BITS (0),
    .MCFILENAME ("parser_smdata.mem"),
    .VRFILENAME ("parser_vardata.mem"),
    .STANDALONE (1)
    ) parser_machine  (
    .variables(variables),
    .states(states),
//    .interrupt(interrupt),
    .interrupt(0),
    .interrupt_address(interrupt_address),
    .hlt(hlt),
    .rst(rst),
    .ready(ready),
    .debug_adr(debug_adr),
    .clk(clk)
);


endmodule
