// Copyright (c) 2021-2022 HotWright Inc.
// Created Fri Dec 16 10:26:59 2022

// This is a machine generated file do not edit!
// copy it to another file name and use that in a design
// this file will be over written


module parserRL_sm(
    input din0,
    input din1,
    input din2,
    input din3,
    input din4,
    input din5,
    input din6,
    input din7,
    input cr_wrap_around,
    input valid,
    input clk,
    input hlt,
    input rst,
    input var_tvalid,
    input var_tdata,
    input sm_tvalid,
    input [23:0] sm_tdata,
    input interrupt,
    input [4:0] interrupt_address,
    output pop,
    output push,
    output cr_data,
    output [4:0] debug_adr,
    output ready);


wire [2:0] states;
wire [9:0] variables;

assign pop = states[0];
assign push = states[1];
assign cr_data = states[2];


assign variables = { valid, cr_wrap_around, din7, din6, din5, din4, din3, din2, din1, din0 };


hotstate #(
    .NUM_STATES (3),
    .NUM_VARS (10),
    .NUM_VARSEL (6),
    .NUM_VARSEL_BITS (3),
    .NUM_TIMERS (0),
    .NUM_ADR_BITS (5),
    .NUM_CTL_BITS (18),
    .NUM_WORDS (24),
    .STACK_DEPTH (0),
    .NUM_SWITCHES (0),
    .SWITCH_MEM_WORDS (0),
    .NUM_SWITCH_BITS (1),
    .SWITCH_OFFSET_BITS (0),
    .STANDALONE (0)
    ) parserRL_machine  (
    .variables(variables),
    .states(states),
    .sm_tdata(smdata_word),
    .sm_tvalid(sm_tvalid),
    .var_tdata(vardata_bit),
    .var_tvalid(var_tvalid),
    .interrupt(interrupt),
    .interrupt_address(interrupt_address),
    .hlt(hlt),
    .rst(rst),
    .ready(ready),
    .debug_adr(debug_adr),
    .clk(clk)
);


endmodule
