`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 11/14/2022 03:49:14 PM
// Design Name: 
// Module Name: bram_test
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module bram_test(
    input [63:0] data,
    input read_en,
    input clk, 
    output [7:0] parse_data,
    output valid
    );
    
    reg [63:0] captured_data;
    
    always @(posedge clk) begin
    
    captured_data <= data;
    
    end
    assign parse_data = captured_data[7:0];
    assign valid = read_en;
    
endmodule
