`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Hotwright Inc.
// Engineer: Steve Casselman
// 
// Create Date: 12/31/2022 03:24:20 AM
// Design Name: 
// Module Name: reg 
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Crea:ted
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module reg_n#(parameter BUSSIZE = 64)
    (
    input [BUSSIZE -1: 0] data_in,
    input valid,
    input rst,
    input clk,
    output [BUSSIZE -1: 0] data_out
    );
    reg [BUSSIZE -1: 0] data_out;
    always @(posedge clk) begin
    if (rst == 1) data_out <= 0;
    else if (valid == 1) data_out <= data_in;
    end
endmodule
