// Copyright (c) 2021-2022 HotWright Inc.
// Created Fri Dec 10 02:47:52 2021

// This is a machine generated file do not edit!
// copy it to another file name and use that in a design
// this file will be over written


module parser_sm(
/*    input in0,
    input in1,
    input in2,
    input in3,
    input in4,
    input in5,
    input in6,
    input in7,
*/
    input [7:0] in, 
    input next_wrap_around,
    input clk,
    input hlt,
//    input var_tvalid,
//    input var_tdata,
//    input sm_tvalid,
//    input [23:0] sm_tdata,
    input interrupt,
    input [4:0] interrupt_address,
    output read_data,
    output write_data,
    output next,
    output ready);


wire [2:0] states;
wire [8:0] variables;

assign read_data = states[0];
assign write_data = states[1];
assign next = states[2];

wire next_wrap_around ;
/*wire in7 ;
wire in6 ;
wire in5 ;
wire in4 ;
wire in3 ;
wire in2 ;
wire in1 ;
wire in0 ;
*/
wire [7:0] in;


assign variables = { next_wrap_around, in[7:0]};//in7, in6, in5, in4, in3, in2, in1, in0 };


hotstate #(
    .NUM_STATES (3),
    .NUM_VARS (9),
    .NUM_VARSEL (4),
    .NUM_VARSEL_BITS (3),
    .NUM_TIMERS (0),
    .NUM_ADR_BITS (5),
    .NUM_CTL_BITS (18),
    .NUM_WORDS (17),
    .STACK_DEPTH (0),
    .NUM_SWITCHES (0),
    .SWITCH_MEM_WORDS (0),
    .NUM_SWITCH_BITS (1),
    .SWITCH_OFFSET_BITS (0),
    .STANDALONE (1)
    ) parser_machine  (
    .variables(variables),
    .states(states),
    .interrupt(interrupt),
    .interrupt_address(interrupt_address),
    .hlt(hlt),
    .rst(rst),
    .ready(ready),
    .clk(clk)
);

initial begin

$readmemh("parser_smdata.mem",parser_sm.parser_machine.Microcode.code,0,16);
$readmemb("parser_vardata.mem",parser_sm.parser_machine.variable.Variable.code,0,2047);
end


endmodule
